Compression-Aware Pseudo-Functional Testing

With technology scaling, the discrepancy between integrated circuits' activities in normal functional mode and that in structural test mode has an increasing adverse impact on the effectiveness of manufacturing test. By identifying functionally unreachable states in the circuit and avoiding them during the test generation process, pseudo-functional testing is an effective technique to address this problem. Pseudo-functional patterns, however, feature much less don't-care bits when compared to conventional structural patterns, making them less friendly to test compression techniques. In this paper, we propose novel solutions to address the above problem, which facilitate to apply pseudo-functional testing in linear decompressor-based test compression environment. Experimental results on ISCAS'89 benchmark circuits demonstrate the effectiveness of the proposed methodology.