Multistage switching architectures for software routers

被引:15
|
作者
Bianco, Andrea [1 ]
Finochietto, Jorge M. [1 ]
Mellia, Marco [1 ]
Neri, Fabio [1 ]
di Torino, Politecnico [1 ]
Galante, Giulio [1 ]
机构
[1] Politecn Torino, Dept Elect, Turin, Italy
来源
IEEE NETWORK | 2007年 / 21卷 / 04期
关键词
D O I
10.1109/MNET.2007.386465
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Software routers based on personal computer (PC) architectures are becoming an important alternative to proprietary and expensive network devices. However, software routers suffer from many limitations Of the PC architecture, including, among others, limited bus and central processing unit (CPU) bandwidth high memory access latency, limited scalability in terms of number of network interface cards, and lack of resilience mechanisms. Multistage PC-based architectures can be an interesting alternative since they permit us to i) increase the performance of singlesoftware routers, ii) scale router size, iii) distribute packet-manipulation and control functionality, iv) recover from single-component failures, and v) incrementally upgrade router performance. We propose a specific multistage architecture, exploiting PC-based routers as switching elements, to build a high-speed, largesize, scalable, and reliable software router. A small-scale prototype of the multistage router is currently up and running in our labs, and performance evaluation is un er way.
引用
收藏
页码:15 / 21
页数:7
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