Framework for executing VHDL code on FPGA

In previous work [1,2], we have explored the application of FPGA (Field Programmable Gate Array[6]) technology to fractal image compression, matrix multiplication, and recursive fractal image decompression. All of these applications share similar characteristics of design, deploy onto FPGA hardware, and then test the configuration to make sure the approach is feasible. We are now taking into consideration the usefulness of the FPGA platform as a technology for integration of specialized hardware into software design (co-design). Since hardware solutions are inherently faster than purely software solutions there should be a mechanism to execute hardware based solutions through software in a reconfigurable nature. Today there are many solutions for modeling and deploying FPGA hardware and simulating VDHL in software, but there are no general purpose software solutions that can be commercially deployed. In this project, we are working on developing a general purpose FPGA framework that software programmers can use to run VHDL (verilog hardware definition language) developed algorithms, without having to write complex device drivers, and specialized interfaces. The framework will support the PCI bus specification and provide a mechanism for programming, simulating, and streaming information to and from the FPGA hardware[8].