Low-Complexity Architecture of RS Decoder for CMMB System

Based on the Berlekamp-Massey algorithm, a low-complexity VLSI architecture of Reed-Solomon decoder for CMMB is presented in this paper. The proposed scheme has a folded systolic architecture, in which both error-locator and the error-evaluator can be computed in a single array of processors. With the folding property of the systolic array architecture, the number of the multipliers and the adders are reduced drastically. The architecture chooses 8 as the folding factor, as a result, 80% fewer multipliers and adders are used in the proposed architecture than in the RiBM architecture. The reduction in the number of multipliers and adders lead to smaller silicon area and lower power consumption. The proposed RS (240,224) decoder design is implemented and fabricated in HJTC 0.18 mu m 1P6M CMOS technology.(1)