Low-power optimization techniques for BDD mapped circuits using temporal correlation

In modern design flows low-power aspects should be considered as early as possible to minimize power dissipation in the resulting circuit. A new binary decision diagram-based design style that considers switching activity optimization using temporal correlation information is presented. The technique is based on an approximation method for switching activity estimation. In the case of finite state machines, the presented method extracts signal statistics by means of Markov chain analyses. Experimental results on a set of MCNC and ISCAS89 benchmarks show the estimated reduction in power dissipation.