Non-overlapping set of efficient assertions

Assertions-based verification (ABV) has become an important step in the validation of complex systems. Therefore writing assertions in an efficient manner could be a concern particularly when assertions are implemented and synthesized in the design. In this paper, we introduce a method on how to find a minimum set of necessary assertions and to eliminate the redundant ones. An algorithm is developed for writing non-overlapping assertions. We tested this approach on SAYEH design, a non pipelined processor where we added several embedded assertions. Experimental results show the feasibility of this approach.