A 283 GHz low power heterodyne receiver with on-chip local oscillator in 65 nm CMOS process

被引：0

作者：

Guerra, Jose Moron ^{[1
,2
]}

Siligaris, Alexandre ^{[1
]}

Lampin, Jean-Francois ^{[2
]}

Danneville, Francois ^{[2
]}

Vincent, Pierre ^{[1
]}

机构：

[1] CEA, LETI, MINATEC, 17 Rue Martyrs, F-38054 Grenoble, France

[2] CNRS, IEMN, F-59652 Villeneuve Dascq, France

来源：

2013 IEEE RADIO FREQUENCY INTEGRATED CIRCUITS SYMPOSIUM (RFIC) | 2013年

关键词：

mmW; Heterodyne receiver; Sub-harmonic injection locked oscillator; THz; sub-THz; CMOS; RESISTIVE MIXER;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A Fully integrated 283 GHz heterodyne receiver in 65 nm CMOS process is presented in this paper. The circuit includes a resistive differential mixer, an intermediate frequency amplifier and a 282 GHz sub-harmonic injection locked oscillator. The on-chip oscillator generates a 94 GHz fundamental tone but exploits a 282 GHz third harmonic. An injection signal of 47 GHz (one sixth of the RF frequency) is used to lock the oscillator on a reference. The receiver measured conversion gain is -6 dB for a DC power consumption of 97.6 mW. Simulated noise figure is 38 dB. The chip size is 820 mu m x 780 mu m including matching networks and DC/RF pads.

引用

页码：301 / 304

页数：4

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