Design consideration of 6.25 Gbps signaling for high-performance server

被引：0

作者：

Jiang, Jian Hong ^{[1
]}

Gai, Weixin ^{[1
]}

Hattori, Akira ^{[1
]}

Hidaka, Yasuo ^{[1
]}

机构：

[1] Fujitsu Labs Amer Inc, Platform Innovat Grp, 1240 E Arques Ave, Sunnyvale, CA 94085 USA

来源：

PROCEEDINGS OF THE ASP-DAC 2007 | 2007年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

As network data rate increases rapidly, high-speed signaling circuits for server communication pose many design challenges due to various system requirements using different interconnect mediums. This paper discusses main problems and solutions of high-speed circuits for server interconnect. Then, it presents a high-speed circuit implementation for such interconnect using 90nm CMOS technology that achieved data rate at 6.25 Gbps in a backplane environment.

引用

页码：854 / +

页数：2

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