Design and comparative analysis of SRAM array using low leakage controlled transistor technique with improved delay

Static random access memory power and speed dissipation are the significant factor in most of the electronic applications, which prompts numerous plans with the power utilization of limiting the power during the hold, write, and read processes. One of the important parts of CMOS IC (complementary metal oxide semiconductor integrated circuit) is the memory. The aim of the paper is to consider the current leakage power procedures, where a super low power and low voltage SRAM is planned utilizing every approach. By doing the memory cell analysis, an unmistakable thought has been taken, and two new memory cells are proposed. An array of 16 x 16 SRAM array structure is designed using SRAM, sense amplifier, address and column decoder has been designed. In this article, the projected SRAM cell scheme is able to diminish the leakage power dissipation. To determine schematic solutions and to analyze power dissipation, delay and PDP (power delay product), Tanner EDA (electronic design automation) tool is used. The design techniques and the results have been analyzed at various nanometer technologies with the use of industrial standard library files. A comparison table has been taken to analyze the various parameters of the existing to the proposed design. Based on the results obtained, it is found that there is 53.63% and 47.81% decrease in power dissipation without any performance destruction in the memory cell level approaches and array structures.