Design of a Double-Gate Power LDMOS With Improved SOA by Complementary Majority Carrier Conduction Paths

An n-type power LDMOS with an integrated pMOS is proposed to improve the safe operation area. The proposed structure has three external terminals and majority carriers of both types are used for conduction under high-voltage and high-current condition. The p-MOS is implemented outside of the voltage-sustaining region of the n-MOS. Under high-voltage and high-current condition, the gate of the p-MOS is turned ON by a self-generated negative gate-to-source voltage. Majority hole current from p-MOS is introduced into the p-top region. It alters the electric field profile in the voltage-sustaining region and reduces impact ionization. As a result, the output I-V curves become flatter and the saturation current is more than twice of that of a conventional n-MOS with the same breakdown voltage at V-GS >= 8V.