Clock-deskew buffer using a SAR-Controlled delay-locked loop

被引：71

作者：

Dehng, GK ^{[1
]}

Hsu, JM ^{[1
]}

Yang, CY ^{[1
]}

Liu, SI ^{[1
]}

机构：

[1] Natl Taiwan Univ, Dept Elect Engn, Taipei 106, Taiwan

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2000年 / 35卷 / 08期

关键词：

clock skew; lock time; PVTL; SARDLL; static phase error;

D O I：

10.1109/4.859501

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A successive approximation register-controlled delay-locked loop (SARDLL) has been fabricated in a 0.25-mu m standard n-well DPTM CMOS process to realize a fast-lock clock-deskew buffer for long distance clock distribution, This DLL adopts a binary search method to shorten lock time while maintaining tight synchronization between input and output clocks. The measured lock time of the proposed SARDLL is within 30 clock cycles at 100-MHz clock input. The power dissipation is 3.3 mW (not including off-chip driver's) at a 1.1-V supply voltage while the measured rms and peak-to-peak jitter are 11.3 ps and 95 ps, respectively.

引用

页码：1128 / 1136

页数：9

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