Design and implementation of fiber channel data analyzer

被引:0
|
作者
Archana, S. [1 ]
Hiremath, Sujatha [1 ]
Kumar, Pradeep B. [2 ]
Ananda, C. M. [2 ]
机构
[1] RV Coll Engn, Dept Elect & Commun Engn, Bangalore, Karnataka, India
[2] CSIR Natl Aerosp Labs, Aerosp Elect & Syst Div, Bangalore, Karnataka, India
关键词
Fiber Channel; Protocol Analyzer; FPGA; GUI;
D O I
暂无
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
Most of the systems rely on Fiber Channel link to stream large volumes of varied data at high speed and low latency. Due to the critical nature of these systems, verifying the data flow in the network is vital and hence avoiding transfer of deluding or false data that may prompt hazardous conditions in the system. This paper describes a design for a custom made protocol analyzer that receives, decodes, displays and validates the data transmission over the Fiber Channel. The protocol analyzer consists of a receiver block implemented on Xilinx Spartan 6 board which is interfaced to a customised GUI implemented on a Host PC on windows platform. As a case study, the paper describes the application of the proposed analyzer system with Avionics Digital Video Bus (ADVB) protocol that transmits video data with a video resolution of 1400x1050 (SXGA+) RGB at a standard link rate of 3.1875Gbps. At an instance the analyzer can capture and analyse a defined length of data in ADVB frame. The results of case study show the detailed data types and error status of each decoded ADVB frame.
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页数:6
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