A 13-bit 1-MS/s SAR ADC With Rotation-Based Mismatch Error Cancellation

This paper presents a mismatch error cancellation technique for high-resolution successive approximation register (SAR) analog-to-digital converter (ADC). The proposed technique that combines residue voltage oversampling and capacitors rotation significantly diminishes the impact of capacitor mismatch without calibration. A VCO-based comparator is adopted to achieve good noise performance with high energy efficiency. A 13-bit 1-MS/s SAR ADC is designed in a 180-nm CMOS technology to prove this technique. The post-layout simulated SAR ADC consumes 154.45 mu W, achieves SNDR of 75.25 dB and SFDR of 90.34 dB at Nyquist input, resulting in a Schreier figure of merit (FoM) of 170.35 dB.