A 0.1-1.5G SDR Transmitter with Two-Stage Harmonic Rejection Power Mixer in 65-nm CMOS

被引：0
|
作者：
Lyu, Bing [1 ]
Yin, Yun [1 ]
Yu, Xiaobao [1 ]
Chi, Baoyong [1 ]
机构：
[1] Tsinghua Univ, Inst Microelect, Beijing 100084, Peoples R China
来源：
PROCEEDINGS OF 2015 IEEE 11TH INTERNATIONAL CONFERENCE ON ASIC (ASICON) | 2015年
基金：
中国国家自然科学基金;
关键词：
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
A 0.1-1.5GHz Software-Defined Radio (SDR) transmitter has been implemented in 65nm CMOS. To solve the harmonic-mixing issue, a proposed two-stage harmonic rejection (HR) power mixer is integrated in the transmitter, which can directly drive the power amplifier. The first-stage and second-stage HR work in current mode, via current mirror and current division circuits respectively, different from other harmonic rejection methods. With the maximum gain RF I-to-V conversion, the simulated conversion gain of the power mixer ranges from 13.2 to 16dB. The proposed power mixer achieves > 65dB HRR3 and > 68dB HRR5, respectively, over the covered frequency band without any calibration in various process corners. The simulated OP1dB is between 9.4dB and 12.3dB, large enough to drive the following PA.
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页数：4
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