32 GHz 6.5 mW Gate-Level-Pipelined 4-bit Processor using Superconductor Single-Flux-Quantum Logic

被引：27

作者：

Ishida, Koki ^{[1
]}

Tanaka, Masamitsu ^{[2
]}

Nagaoka, Ikki ^{[2
]}

Ono, Takatsugu ^{[1
]}

Kawakami, Satoshi ^{[1
]}

Tanimoto, Teruo ^{[1
]}

Fujimaki, Akira ^{[2
]}

Inoue, Koji ^{[1
]}

机构：

[1] Kyushu Univ, Fukuoka, Japan

[2] Nagoya Univ, Nagoya, Aichi, Japan

来源：

2020 IEEE SYMPOSIUM ON VLSI CIRCUITS | 2020年

关键词：

D O I：

10.1109/vlsicircuits18222.2020.9162826

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A Single-Flux-Quantum (SFQ) 4-bit throughput-oriented processor has successfully been demonstrated at up to 32 GHz with the measured power consumption of 6.5 mW. This is the first implementation of the gate-level-pipelined processor, and it achieves 2.5 Tera-Operations Per Watt (TOPS/W) by circuit and architectural optimizations.

引用

页数：1

共 15 条

[1] A 48GHz 5.6mW Gate-Level-Pipelined Multiplier Using Single-Flux Quantum Logic
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2019 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE (ISSCC), 2019, 62 : 460 - +
[2] Investigation of timing margin in single-flux-quantum 4 bit adders for increasing clock frequency of gate-level-pipelined circuits
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[3] 4-BIT RAPID SINGLE-FLUX-QUANTUM DECODER
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SEMENOV, VK
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NANDAKUMAR, V
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[4] 50-GFLOPS Floating-Point Adder and Multiplier Using Gate-Level-Pipelined Single-Flux-Quantum Logic With Frequency-Increased Clock Distribution
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[5] Demonstration of an Energy-Efficient, Gate-Level-Pipelined 100 TOPS/W Arithmetic Logic Unit Based on Low-Voltage Rapid Single-Flux-Quantum Logic
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Tanaka, Masamitsu
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2019 IEEE INTERNATIONAL SUPERCONDUCTIVE ELECTRONICS CONFERENCE (ISEC), 2019,
[6] 4-bit Bipolar Triangle Voltage Waveform Generator Using Single-Flux-Quantum Circuit
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Takahashi, Yoshitaka
Shimada, Hiroshi
Maezawa, Masaaki
Mizugaki, Yoshinao
PROCEEDINGS OF THE 27TH INTERNATIONAL SYMPOSIUM ON SUPERCONDUCTIVITY (ISS 2014), 2015, 65 : 213 - 216
[7] 100 GHz operation of a 4-bit single-flux-quantum pulse-frequency modulator designed for bipolar D/A conversion
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Shimada, Hiroshi
IEICE ELECTRONICS EXPRESS, 2022, 19 (12)
[8] Three Parallel Generation of a 4-bit M-Sequence Using Single-Flux-Quantum Digital Circuits
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Mutoh, Yasuaki
Urai, Yoshiaki
Sawada, Kazunao
Watanabe, Tomoki
2015 15TH INTERNATIONAL SUPERCONDUCTIVE ELECTRONICS CONFERENCE (ISEC), 2015,
[9] Three Parallel Generation of a 4-bit M-Sequence Using Single-Flux-Quantum Digital Circuits
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[10] Lowering Latency in a High-Speed Gate-Level-Pipelined Single Flux Quantum Datapath Using an Interleaved Register File
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