共 50 条
- [1] Efficient scan chain design for power minimization during scan testing under routing constraint INTERNATIONAL TEST CONFERENCE 2003, PROCEEDINGS, 2003, : 488 - 493
- [2] Multiple Scan Trees Synthesis for Test Time/Data and Routing Length Reduction under Output Constraint 2009 ASIAN TEST SYMPOSIUM, PROCEEDINGS, 2009, : 231 - 236
- [5] An Improved Scan Design for Minimization of Test Power under Routing Constraint 2015 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2015, : 629 - 632
- [6] Multi-mode-segmented scan architecture with layout-aware scan chain routing for test data and test time reduction IET COMPUTERS AND DIGITAL TECHNIQUES, 2008, 2 (06): : 434 - 444
- [7] Multi-mode segmented scan architecture with layout-aware scan chain routing for test data and test time reduction PROCEEDINGS OF THE 15TH ASIAN TEST SYMPOSIUM, 2006, : 225 - +
- [8] Test scheduling and scan-chain division under power constraint 10TH ASIAN TEST SYMPOSIUM, PROCEEDINGS, 2001, : 259 - 264
- [9] Power reduction in test-per-scan BIST with supply gating and efficient scan partitioning 6TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, PROCEEDINGS, 2005, : 453 - 458
- [10] On test data volume reduction for multiple scan chain designs 20TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS, 2002, : 103 - 108