Eager Recirculating Memory to Alleviate the Von Neumann Bottleneck

被引:0
|
作者
Edwards, Jonathan [1 ]
O'Keefe, Simon [1 ]
机构
[1] Univ York, York Ctr Complex Syst Anal, York, N Yorkshire, England
关键词
NEURAL-NETWORKS;
D O I
暂无
中图分类号
TP18 [人工智能理论];
学科分类号
081104 ; 0812 ; 0835 ; 1405 ;
摘要
This paper presents an examination of channel based time delays and their application as units which perform storage and computation. We describe the implementation of compound arithmetic operations, and show that by re-circulating the impulses along a channel, both memory and computation can be achieved on the same general channel unit. In addition, this approach has the further advantage of performing arithmetic simplification eagerly, so that the resultant use of memory is optimised by the intermediate processing during memory circulation phases.
引用
收藏
页数:5
相关论文
共 50 条
  • [1] Breaking the von Neumann bottleneck: architecture-level processing-in-memory technology
    Zou, Xingqi
    Xu, Sheng
    Chen, Xiaoming
    Yan, Liang
    Han, Yinhe
    SCIENCE CHINA-INFORMATION SCIENCES, 2021, 64 (06)
  • [2] Breaking the von Neumann bottleneck: architecture-level processing-in-memory technology
    Xingqi Zou
    Sheng Xu
    Xiaoming Chen
    Liang Yan
    Yinhe Han
    Science China Information Sciences, 2021, 64
  • [3] Breaking the von Neumann bottleneck:architecture-level processing-in-memory technology
    Xingqi ZOU
    Sheng XU
    Xiaoming CHEN
    Liang YAN
    Yinhe HAN
    Science China(Information Sciences), 2021, 64 (06) : 60 - 69
  • [4] The Von Neumann Bottleneck in Photonic Tensor Core Systems
    Schwartz, Russell L. T.
    Yang, Hangbo
    Peserico, Nicola
    Sorger, Volker J.
    2024 IEEE PHOTONICS SOCIETY SUMMER TOPICALS MEETING SERIES, SUM 2024, 2024,
  • [5] The Reduceron: Widening the von Neumann bottleneck for graph reduction using an FPGA
    Naylor, Matthew
    Runciman, Colin
    IMPLEMENTATION AND APPLICATION OF FUNCTIONAL LANGUAGES, 2008, 5083 : 129 - 146
  • [6] ndn∥mem : an Architecture to Alleviate the Memory Bottleneck for Named Data Networking
    Rezazad, Mostafa
    Tay, Y. C.
    CONEXT STUDENT WORKSHOP '13, 2013, : 1 - 3
  • [7] A Characterization of von Neumann Games in Terms of Memory
    Giacomo Bonanno
    Synthese, 2004, 139 : 281 - 295
  • [8] A characterization of von Neumann games in terms of memory
    Bonanno, G
    SYNTHESE, 2004, 139 (02) : 281 - 295
  • [9] Routing Brain Traffic Through the Von Neumann Bottleneck: Parallel Sorting and Refactoring
    Pronold, Jari
    Jordan, Jakob
    Wylie, Brian J. N.
    Kitayama, Itaru
    Diesmann, Markus
    Kunkel, Susanne
    FRONTIERS IN NEUROINFORMATICS, 2022, 15
  • [10] A Single-Stage RISC-V Processor to Mitigate the Von Neumann Bottleneck
    Kanamoto, Toshiki
    Fukushima, Masami
    Kitagishi, Koichi
    Nakayama, Seijin
    Ishihara, Hideki
    Kasai, Koki
    Kurokawa, Atsushi
    Imai, Masashi
    2019 IEEE 62ND INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS), 2019, : 1085 - 1088