A reconfigurable 0.18-μm CMOS equalizer IC with an improved tunable delay-line for 10-Gb/sec backplane serial I/O links

被引：3
|
作者：
Bien, Franklin [1 ]
Kim, Hyoungsoo [1 ]
Hur, Youngsik [1 ]
Maeng, Moonkyun [1 ]
Gebara, Edward [1 ,2 ]
Laskar, Joy [1 ,2 ]
机构：
[1] Georgia Inst Technol, Sch Elect & Comp Engn, GEDC, 85 5th St NW, Atlanta, GA 30332 USA
[2] Quellan Inc, Atlanta, GA USA
来源：
2006 IEEE MTT-S INTERNATIONAL MICROWAVE SYMPOSIUM DIGEST, VOLS 1-5 | 2006年
关键词：
backplane; CMOS; FFE; FIR filter; tunable delay-line; reconfigurable equalizer; 10Gb/sec;
D O I：
10.1109/MWSYM.2006.249617
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
In this paper, a reconfigurable CMOS equalizer is presented to accommodate vast variety of backplane channel loss characteristics. Backplane channels over different trace lengths and dielectric materials were measured and characterized. Feed-Forward Equalizer (FFE) topology with Finite Impulse Response (FIR) architecture was chosen for optimal equalization for the corresponding backplane configurations. For a reconfigurable FFE IC implementation, Wide-range tunable delay-line (15-ps similar to 74-ps) and variable tap-gain amplifier were fabricated in a 0.18-mu m standard CMOS technology. The proposed reconfigurable FFE demonstrated successful equalization at 10Gb/sec over various channel configurations with 26mW power dissipation from a 1.8-V supply.
引用
收藏
页码：490 / 493
页数：4
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