Hardware Implementation of Motion Estimation Using a Sub-sampled Block for Frame Rate Up-Conversion

In this paper, we present a new motion estimation hardware architecture using a sub-sampled block, which can be used for frame rate up-conversion. The proposed architecture provides the advantage of reducing computational hardware complexity greatly, compared to the conventional architecture, while maintaining the quality of interpolated images. FPGA implementation shows that the proposed motion estimation hardware architecture reduces the hardware size by 51 %, compared to the conventional architecture at the cost of average PSNR degradation of only 0.22bB for interpolated images.