A true random number generator architecture based on a reduced number of FPGA primitives

This paper reports on the design, realization and characterization of a True Random Number Generator (TRNG) that operates using as seeds of entropy, the jitter and the metastability introduced by primitives of a Field Programmable Gate Arrays (FPGA) board. In particular, the TRNG architecture has been implemented on a Xilinx Ultrascale XCKU040 FPGA board. Generally, the implementations on FPGA of fully digital TRNGs make use of ring oscillators employing a large number of Look-Up-Table (LUT) blocks. Differently from this approach, this paper demonstrates that a reliable FPGA-based TRNG architecture can be realized mainly employing only a single PLL and three on-board primitives together with other few basic logic elements (i.e., 8 D-type Flip-Flop, 17 LUT and 2 Counters) used only for the initial overall system synchronization and post-processing operations. In this way, the proposed solution largely reduces the employed number of the FPGA Configurable Logic Blocks (CLB), the circuitry complexity and the overall power consumption without affecting the achievable output bit rate so resulting suitable for full-custom VLSI implementations. The random and statistical properties of the generated 100 Mbps output bitstreams have been validated by passing all the National Institute of Standards and Technology (NIST) tests as well as the Anderson-Darling and the Kolmogorov-Smirnov tests so demonstrating that the proposed TRNG architecture can be suitably employed in security/cybersecurity network systems as well as, once integrated, in Internet-of-Things (loT) and Industrial-Internet-of-Things (IIoT) applications. (C) 2019 Elsevier GmbH. All rights reserved.