Novel Shared Multiplier Scheduling Scheme for Area-Efficient FFT/IFFT Processors

被引：4

作者：

Kim, Eun Ji ^{[1
]}

Lee, Jea Hack ^{[2
]}

Sunwoo, Myung Hoon ^{[2
]}

机构：

[1] Samsung Elect Co Ltd, Suwon 442600, South Korea

[2] Ajou Univ, Dept Elect & Comp Engn, Suwon 443749, South Korea

来源：

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | 2015年 / 23卷 / 09期

基金：

新加坡国家研究基金会;

关键词：

Fast Fourier transform (FFT); mixed-radix multipath delay commutator (MRMDC); optical orthogonal frequency-division multiplexing (O-OFDM); ultrawideband (UWB); wireless personal area network (WPAN); FFT PROCESSOR; LOW-POWER; OFDM TRANSMISSION;

D O I：

10.1109/TVLSI.2014.2347399

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper proposes a shared multiplier scheduling scheme (SMSS) for area-efficient fast Fourier transform (FFT)/inverse FFT processors. SMSS can significantly reduce the total number of complex multipliers up to 28%. The proposed mixed-radix multipath delay commutator processors can support 128/256 and 256/512-point FFTs using SMSS. The proposed processors have been designed and implemented with 90-nm CMOS technology, which can reduce the total hardware complexity by 20%. The proposed processors having eight-parallel data paths can achieve a high throughput rate up to 27.5 GS/s at 430 MHz. In addition, the proposed processors can support any FFT size using additional stages.

引用

页码：1689 / 1699

页数：11

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