Heterogeneous Multi-Die Stitching Enabled by Fine-Pitch and Multi-Height Compressible Mircointerconnects (CMIs)

被引：11

作者：

Jo, Paul K. ^{[1
]}

Zhang, Xuchen ^{[1
]}

Gonzalez, Joe L. ^{[1
]}

May, Gary S. ^{[2
,3
]}

Bakir, Muhannad S. ^{[1
]}

机构：

[1] Georgia Inst Technol, Sch Elect & Comp Engn, Atlanta, GA 30332 USA

[2] Georgia Inst Technol, Atlanta, GA 30332 USA

[3] Univ Calif Davis, Davis, CA 95616 USA

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 2018年 / 65卷 / 07期

基金：

美国国家科学基金会;

关键词：

2.5-D/3-D package assembly; compliant interconnects; heterogeneous integration; system in package (SiP); SILICON; DESIGN; FABRICATION; TSV;

D O I：

10.1109/TED.2018.2838529

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A high-density and a highly scalable heterogeneous multi-die integration technology is presented in this paper. Central to this approach is a dense and face-to-face integration of heterogeneous ICs enabled by fine-pitch and multi-height compressible microinterconnects (CMIs) and stitch chips, which serve as the interface through which communication between active ICs occurs. Two separate testbeds are fabricated in order to characterize the proposed integration technology: the first testbed demonstrates the concatenated assembly of chips using the stitch chips with fine-pitch CMIs (in-line pitch of 20 mu m), while the second testbed demonstrates the fabrication of multi-height CMIs (75-, 55-, and 30-mu m tall CMIs) on the same die. Electrical characterization, including resistance and S-parameters, and mechanical characterization of interconnects are reported as well as the assembly of the testbeds.

引用

页码：2957 / 2963

页数：7

共 5 条

[1] Polylithic Integration of 2.5-D and 3-D Chiplets Enabled by Multi-Height and Fine-Pitch CMIs
Jo, Paul K.
Kochupurackal Rajan, Sreejith
Gonzalez, Joe L.
Bakir, Muhannad S.
IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, 2020, 10 (09): : 1474 - 1481
[2] Heterogeneous Interconnect Stitching Technology With Compressible MicroInterconnects for Dense Multi-Die Integration
Zhang, Xuchen
Jo, Paul K.
Zia, Muneeb
May, Gary S.
Bakir, Muhannad S.
IEEE ELECTRON DEVICE LETTERS, 2017, 38 (02) : 255 - 257
[3] Multi-Die Polylithic Integration Enabled by Heterogeneous Interconnect Stitching Technology (HIST)
Jo, Paul K.
Zheng, Ting
Bakir, Muhannad S.
2018 IEEE 27TH CONFERENCE ON ELECTRICAL PERFORMANCE OF ELECTRONIC PACKAGING AND SYSTEMS (EPEPS), 2018, : 11 - 13
[4] Heterogeneous Multi-Die Stitching: Technology Demonstration and Design Considerations
Jo, Paul K.
Hossen, Md Obaidul
Zhang, Xuchen
Zhang, Yang
Bakir, Muhannad S.
2018 IEEE 68TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC 2018), 2018, : 1512 - 1518
[5] Thru Silicon Via Stacking & Numerical Characterization for Multi-Die Interconnections using Full Array & Very Fine Pitch Micro C4 Bumps
Au, K. Y.
Beleran, J. D.
Yang, Y. B.
Zhang, Y. F.
Kriangsak, S. L.
Wilson, P. L. Ong
Drake, Y. S. Koh
Toh, C. H.
Surasit, C.
2011 IEEE 61ST ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC), 2011, : 296 - 303

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