A VHDL-based approach for power estimation of embedded systems

Power dissipation has become one of the main constraints during the design of embedded systems and VLSI circuits in the recent years, due to continuous increase of the integration level and the operating frequency. The aim of this paper is to present an innovative conceptual framework suitable for achieving accurate and efficient estimation of power dissipation for embedded systems described in VHDL at the behavioral and Register-Transfer levels. The goal is to provide the designer with the capability of analyzing and comparing different solutions in the architectural design space before the synthesis. The analytical power model is hierarchical, considering the different parts of the target system architecture, mainly the data-path, the memory, the control logic and the embedded core processor. Experimental results are obtained by applying the proposed power model to benchmark circuits.