Hierarchical indexing data structure method for verifying the functionality of the STI-to-PCI bridge chips of the IBM eServer z900

被引：0

作者：

Silverio, JF ^{[1
]}

Ng, YM ^{[1
]}

Anderson, DF ^{[1
]}

机构：

[1] IBM Corp, Serv Grp, Poughkeepsie, NY 12601 USA

来源：

IBM JOURNAL OF RESEARCH AND DEVELOPMENT | 2002年 / 46卷 / 4-5期

关键词：

D O I：

10.1147/rd.464.0617

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

The IBM eServer z900 has an overall system I/O bandwidth which is three times that of IBM S/390(R) G5/G6 servers, necessitating the use of Self-Timed-interface (STI)-to-Peripheral-Component-interface (PCI) bridge chips to exploit this bandwidth. The chips are used to form a layer between the networking attachments of the z900 and its main storage complex. The layer adapts the high-speed point-to-point packet-oriented STI interface of the z900 to its multi-drop PCI bus structure. This paper describes a method for verifying the functionality of the STI-to-PCI bridge chips by implementing a hierarchical indexing method to support all address dispatching, data management, and data integrity checking. The method is at the core of the random-element-level verification methodology to support all data movement mainline testing of the z900. Monitors, checkers, and drivers were developed and integrated as part of the overall methodology to verify all external interfaces.

引用

页码：617 / 629

页数：13