44.6% processing cycles reduction in GSM voice coding by low-power reconfigurable co-processor architecture

被引：1
|
作者：
Atzori, E [1 ]
Carta, SM [1 ]
Raffo, L [1 ]
机构：
[1] Univ Cagliari, Dept Elect & Elect Engn, I-09123 Cagliari, Italy
来源：
ELECTRONICS LETTERS | 2002年 / 38卷 / 24期
关键词：
Algorithms - Correlation theory - Digital signal processing - Electric power supplies to apparatus - Global system for mobile communications - Reduced instruction set computing - Voice/data communication systems;
D O I：
10.1049/el:20021019
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A reconfigurable architecture oriented to low-power digital signal processing is presented, synthesised and tested on ETSI-GSM voice coding algorithms. An overall reduction of 44.6% cycles with respect to standard RISC processors is obtained. Such improvement together with locality and temporal correlation allows a reduction of power consumption.
引用
收藏
页码：1524 / 1526
页数：3
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