VLSI design for memory interface of intelligent instruments

被引：0

作者：

Gao, ML ^{[1
]}

Li, L ^{[1
]}

Hu, YH ^{[1
]}

Wang, R ^{[1
]}

机构：

[1] Hefei Univ Technol, Inst VLSI Design, Hefei 230009, Peoples R China

来源：

PROCEEDINGS OF THE FIRST INTERNATIONAL SYMPOSIUM ON INSTRUMENTATION SCIENCE AND TECHNOLOGY | 1999年

关键词：

arbiter; sequencer; state machine;

D O I：

暂无

中图分类号：

TH7 [仪器、仪表];

学科分类号：

0804 ; 080401 ; 081102 ;

摘要：

Memory plays a very important role in all kinds of computer-based measurement, testing, verification or validation systems. In many cases the system integrators have to design an interface between memory devices and other components in the system, and make it silicon implemented This paper introduces a top-level design of VLSI for an arbiter and a sequencer, which is the core of a memory interface. Two state machines are discussed and the transaction safety is emphasized.

引用

页码：396 / 400

页数：5

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