A Derived Circuit Model for Spiral Inductors on Lossy Silicon Substrate

This paper presents a novel approach for deriving a physically meaningful circuit model for multilayered spiral inductors on lossy silicon substrates. The approach starts from a quasi-static Partial Element Equivalent Circuit (PEEC) model. The concept of complex inductance and capacitance is introduced to account for the conductor and dielectric losses. Basic Y-Delta network transformation is employed to "absorb" the insignificant internal nodes of the original PEEC network progressively. The physically meaningful circuit models of two practical inductors fabricated using 0.18 mu m CMOS process are derived to demonstrate the use of the approach for RFIC applications. Excellent agreement of the Q performances as well as the circuit responses of the derived circuit model with those from the measurements over the frequency range from 0.45 GHz to 10 GRz demonstrates the validity and the powerfulness of this new approach.