Statistical Based MQ Arithmetic Coder

Embedded block coding with optimized truncation (EBCOT) is a key algorithm in JPEG 2000 image compression system. Recently, the bit-plane coder architectures are capable of producing symbols at a higher rate than the capability of the existing MQ arithmetic coders. To solve this problem, a design of a multiple-symbol processor for statistical MQ coder architecture on FPGA is proposed. The proposed architecture takes advantage of simplicity of single-symbol architecture while integrates several techniques in order to increase the coding rate (more than one symbol per clock), reduce critical path, thus accelerate the coding speed. The repeated symbol statistics has been analyzed prior to the proposed architecture using lookahead technique. This allows the proposed architecture to support encoding rate of maximum 8 symbols per clock cycle without stalls and without excessively increasing the hardware cost. This helps to accelerate encoding process, which leads to greatly increase throughput. From the experiments, for lossy wavelet transform, the proposed architecture offers high throughput of at least 233.07 MCxD/S with effectively reducing the number of clock cycles more than 35.51%.