A Novel ON Chip LDO voltage regulator in 180nm

被引：0
|
作者：
Rao, Patri Sreehari [1 ]
Krishnaprasad, K. S. R. [1 ]
机构：
[1] Natl Inst Technol, Chip Design Ctr, Warangal, Andhra Pradesh, India
来源：
ICED: 2008 INTERNATIONAL CONFERENCE ON ELECTRONIC DESIGN, VOLS 1 AND 2 | 2008年
关键词：
D O I：
暂无
中图分类号：
TP18 [人工智能理论];
学科分类号：
081104 ; 0812 ; 0835 ; 1405 ;
摘要：
An on chip low drop out voltage regulator that employs a simple fast path and an elegant compensation scheme is presented in this paper. The novelty in this design is that the device parasitic capacitances are exploited for compensation at different loads. The proposed LDO is designed to provide a constant voltage of 1.2V and is implemented in UMC 180 nano meter CMOS technology. The voltage regulator presented improves stability even at lighter loads and enhances line and load regulation while providing reasonably good transient response.
引用
收藏
页码：287 / 292
页数：6
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