Design of a triple pocket multi-gate material TFET structure for low-power applications

In this paper we propose a triple-pocket multi-gate material TFET (TP-TFET) device structure for a low-power and high-performance circuit design. The proposed device structure integrates the good features of both the conventional MOSFET and tunnel FET. This is achieved through three doped pockets and dual work-function gate material on near the source-channel junction. In the proposed device, the ON state conduction mechanism is dominated by an over-the-barrier thermal diffusion of carriers, thereby offering a high-value drive current. On the other hand, the subthreshold conduction mechanism is dominated by the tunnelling of carriers, thereby incurring a very small leakage current and offering a small subthreshold slope. We use 2D TCAD device simulations for the analysis of the TP-TFET and its comparison with the existing pocketed-heterogate TFET (PHG-TFET). We observe that the proposed TFET offers the average subthreshold slope (SSavg) of 2.85 mV dec(-1) and ON current of similar to 230 mu A mu m(-1) as compared to the existing PHG-TFET, which offers SSavg of 44.91 mV dec(-1) and I-ON = similar to 62 mu A mu m(-1). Further, some benchmark circuits are implemented using these devices. A ring oscillator designed using the TP-TFET shows approximately a 6x higher frequency as compared to that designed using the PHG-TFET. The power delay product of the NAND gate and NOR gate obtained using these devices differ by approximately 3x to 20x as the supply voltage is decreased from 1.0 to 0.5 V.