Physical Unclonable Functions for On-Chip Instrumentation Enhancing the security of the internal Joint Test Action Group network

被引：5

作者：

Kumar, Sudeendra K. ^{[1
]}

Satheesh, Naini ^{[2
]}

Mahapatra, Abhishek ^{[3
]}

Sahoo, Sauvagya ^{[1
]}

Mahapatra, K. K. ^{[4
]}

机构：

[1] Natl Inst Technol Rourkela, Hardware Secur, Rourkela, India

[2] Tessolve Semicond, Bangalore, Karnataka, India

[3] Robert Bosch, Bangalore, Karnataka, India

[4] Natl Inst Technol Rourkela, Elect Engn, Rourkela, India

来源：

IEEE CONSUMER ELECTRONICS MAGAZINE | 2019年 / 8卷 / 04期

关键词：

D O I：

10.1109/MCE.2019.2905539

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

[No abstract available]

引用

页码：62 / 66

页数：5

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[Anonymous], 16872014 IEEE

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[5]

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[7] Using Power Clues to Hack IoT Devices The power side channel provides for instruction-level disassembly [J].

Park, Jungmin ;

Tyagi, Akhilesh .

IEEE CONSUMER ELECTRONICS MAGAZINE, 2017, 6 (03) :92-102

[8]

Sahoo DP, 2014, 2014 IEEE INTERNATIONAL SYMPOSIUM ON HARDWARE-ORIENTED SECURITY AND TRUST (HOST), P50, DOI 10.1109/HST.2014.6855567

[9] Test Scheduling in an IEEE P1687 Environment with Resource and Power Constraints [J].

Zadegan, Farrokh Ghani ;

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2011 20TH ASIAN TEST SYMPOSIUM (ATS), 2011, :525-531

[10]

Zygmontowicz D., 2014, P DES AUT TEST EUR

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