Design and Verification of New n-Bit Quantum-Dot Synchronous Counters Using Majority Function-Based JK Flip-Flops

被引:27
|
作者
Angizi, Shaahin [1 ]
Sayedsalehi, Samira [2 ]
Roohi, Arman [3 ]
Bagherzadeh, Nader [4 ]
Navi, Keivan [5 ]
机构
[1] Inst Res Fundamental Sci IPM, Sch Comp Sci, Tehran 1953833511, Iran
[2] Islamic Azad Univ, South Tehran Branch, Dept Comp Engn, Tehran 1777613651, Iran
[3] Univ Cent Florida, Dept Elect Engn & Comp Sci, Orlando, FL 32816 USA
[4] Univ Calif Irvine, Dept Elect Engn & Comp Sci, Irvine, CA 92697 USA
[5] Shahid Beheshti Univ, Nanotechnol & Quantum Comp Lab, Tehran 1983963113, Iran
关键词
Quantum-dot cellular automata; nanoelectronics; majority gate-based design; JK flip-flop; synchronous counter; CELLULAR-AUTOMATA; INHERENT CAPABILITIES; RAM CELL; MEMORY; EFFICIENT; ARCHITECTURES; CIRCUITS; GATE;
D O I
10.1142/S0218126615501534
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Quantum-dot Cellular Automata (QCA) is an attractive nanoelectronics paradigm which is widely advocated as a possible replacement of conventional CMOS technology. Designing memory cells is a very interesting field of research in QCA domain. In this paper, we are going to propose novel nanotechnology-compatible designs based on the majority gate structures. In the first step, this objective is accomplished by QCA implementation of two well-organized JK flip flop designs and in the second step; synchronous counters with different sizes are presented as an application. To evaluate functional correctness of the proposed designs and compare with state-of-the-art, QCADesigner tool is employed.
引用
收藏
页数:17
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