Test Pattern Generation Using Recursive Pseudo Exhaustive Method for Wallace Tree Multiplier

被引：0

作者：

Zode, Pradnya ^{[1
]}

Zode, Pravin ^{[1
]}

Deshmukh, Raghavendra ^{[2
]}

机构：

[1] Yeshwantrao Chavan Coll Engn, Dept Elect Engn, Nagpur, Maharashtra, India

[2] Visvesvaraya Natl Inst Technol, Ctr VLSI & Nanotechnol, Nagpur, Maharashtra, India

来源：

IEEE INDICON: 15TH IEEE INDIA COUNCIL INTERNATIONAL CONFERENCE | 2018年

关键词：

Pseudo Exhaustive testing; Iterative Logic Array; VLSI testing; Design For Test (DFT); PSEUDOEXHAUSTIVE TEST; DESIGN;

D O I：

暂无

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

Testing of multiplier circuit is a complex issue. As the number of test input increases, test patterns will also increase, which will require more area, consequently more time and power. Pseudo exhaustive test generator scheme generates test sets recursively for any value of 'k' which is less than or equal to 'n'. This paper proposes a test pattern generator for Wallace Tree Multiplier using recursive Pseudo-Exhaustive method. 16-bit Wallace Tree multiplier is partitioned into three columns using multiplexers. Each column is tested exhaustively covering all possible combinational faults exhaustively for every k-bit group. As testing is performed in parallel; The proposed scheme reduces the time required for testing of the multiplier.

引用

页数：4

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