Sub-1 V, 4 nA CMOS Voltage References with Digitally-Trimmable Temperature Coefficient

被引：0

作者：

Luong, Peter ^{[1
]}

Christoffersen, Carlos ^{[1
]}

Rossi-Aicardi, Conrado ^{[2
]}

Dualibe, Carlos ^{[3
]}

机构：

[1] Lakehead Univ, Dept Elect Engn, Thunder Bay, ON P7B 5E1, Canada

[2] Univ Republica, Inst Ingn Elect, Montevideo, Uruguay

[3] Univ Mons, Serv Elect & Microelect, B-7000 Mons, Belgium

来源：

2014 IEEE 12TH INTERNATIONAL NEW CIRCUITS AND SYSTEMS CONFERENCE (NEWCAS) | 2014年

关键词：

PPM/DEGREES-C; CIRCUIT;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Two architectures for MOS-only low power voltage references with digitally-trimmable temperature coefficient are proposed in this work. A test chip implements them in a 0.35 mu m CMOS process. A design methodology for both architectures, performance figures and preliminary test results are presented. Each circuit consumes around 4 nA and operates down to 0.95 V or better with a simulated temperature coefficient of 18 ppm/degrees C in the -20 degrees C to 80 degrees C range.

引用

页码：345 / 348

页数：4

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