A silicon-based yield gain evaluation methodology for embedded-SRAMs with different redundancy scenarios

被引：4

作者：

Rondey, E ^{[1
]}

Tellier, Y ^{[1
]}

Borri, S ^{[1
]}

机构：

[1] Altis Semicond, F-91105 Corbeil Essonnes, France

来源：

PROCEEDING OF THE 2002 IEEE INTERNATIONAL WORKSHOP ON MEMORY TECHNOLOGY, DESIGN AND TESTING | 2002年

关键词：

D O I：

10.1109/MTDT.2002.1029764

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Yield improvement is an essential issue for modem high-volume manufacturing CMOS processes. Process yield is particularly low for area-critical designs, such as embedded memories. The use of redundancy structures which replace faulty memory locations with good ones, has a direct impact on the final chip yield. This paper describes an experimental methodology employed to evaluate the yield gain associated with different redundancy approaches and shows how this method can be applied to determine the optimal redundancy configuration which maximizes the number of good dies per wafer, depending on the embedded memory requirements of a specific product.

引用

页码：57 / 61

页数：5

共 2 条

[1] A silicon-based yield gain evaluation methodology for embedded-SRAMs with different redundancy scenarios
Rondey, E
Tellier, Y
Borri, S
PROCEEDINGS OF THE EIGHTH IEEE INTERNATIONAL ON-LINE TESTING WORKSHOP, 2002, : 251 - 255
[2] Environmental impact evaluation-methodology for emerging silicon-based technologies
Somani, Ajay
Gschwend, Philip
White, Sarah Jane
Boning, Duane
Reif, Rafael
PROCEEDINGS OF THE 2006 IEEE INTERNATIONAL SYMPOSIUM ON ELECTRONICS & THE ENVIRONMENT, CONFERENCE RECORD, 2006, : 258 - +

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