An efficient encoding scheme for ultra-fast flash ADC

被引：0

作者：

Choudhury, J ^{[1
]}

Cavanaugh, C ^{[1
]}

Seetharaman, G ^{[1
]}

机构：

[1] Univ Louisiana, Lafayette, LA USA

来源：

2003 IEEE TOPICAL CONFERENCE ON WIRELESS COMMUNICATION TECHNOLOGY | 2003年

关键词：

D O I：

暂无

中图分类号：

TN [电子技术、通信技术];

学科分类号：

0809 ;

摘要：

We propose a design of encoder using robust principle of Programmable Logic Array (PLA). High-speed operation at the range of MHz-GHz is the major goal of flash ADC design. High-speed ADC needs a fast comparator, a high-speed encoder and a fast sample and hold circuit. These three areas of high-speed ADC design need equally careful attention.

引用

页码：38 / 39

页数：2

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