Fault latencies of concurrent checking FSMs

In this paper we introduce concepts. of a potential fault latency and a real fault latency for Finite State Machines (FSMs). The potential latency defines a minimal value of the possible latency for an FSM, while the real latency relates to the certain implementation of the FSM. A method for investigation of latencies for on-line checking FSMs is described. This technique is based on selection of trajectories of the Markov chain, which describes behavior of the fault free FSM as well as the faulty FSM. We also estimate the lowest bound for an average latency. This estimation may be useful at an initial stage of the design when information concerning requirements to the FSM and conditions of its functioning is limited.