Silicon Photonics Packaging for Highly Scalable Optical Interconnects

Big Data and cloud-based applications drive the increasing amount of data traffic between and within data centers. Optical interconnect technology offers a larger bandwidth-distance product, interconnect density and power efficiency as copper based links. Integrated silicon photonics provides a tight integration between the optical functions with electronics on a single silicon die at the competitive cost-level of CMOS technology. All necessary silicon photonic building blocks operating at 1.3 mu m and 1.55 mu m have already been demonstrated. However, one of the remaining challenges is the system- level assembly, including a scalable connectorization scheme for very high optical I/O counts. To overcome this limitation, we demonstrate in this paper a silicon photonic packaging solution using polymer waveguides, which can be routed tightly to the silicon chip edge. As a first step towards this implementation, the optical coupling between a silicon photonics chip and the polymer waveguides is here discussed. The experimental results of the coupling loss and tolerance to misalignments between a silicon waveguide and a single-mode polymer waveguide processed on the chip are reported.