Data-reuse exploration under an on-chip memory constraint for low-power FPGA-based systems

被引:4
|
作者
Liu, Q. [1 ]
Constantinides, G. A. [1 ]
Masselos, K. [2 ]
Cheung, P. Y. K. [1 ]
机构
[1] Univ London Imperial Coll Sci Technol & Med, Dept Elect & Elect Engn, London SW7 2BT, England
[2] Univ Peloponnese, Dept Comp Sci & Technol, Tripolis 22100, Greece
来源
基金
英国工程与自然科学研究理事会;
关键词
EMBEDDED SYSTEMS; PERFORMANCE; ALGORITHM;
D O I
10.1049/iet-cdt.2008.0039
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Contemporary FPGA-based reconfigurable systems have been widely used to implement data-dominated applications. In these applications, data transfer and storage consume a large proportion of the system energy. Exploiting data-reuse can introduce significant power savings, but also introduces the extra requirement for on-chip memory. To aid data-reuse design exploration early during the design cycle, the authors present an optimisation approach to achieve a power-optimal design satisfying an on-chip memory constraint in a targeted FPGA-based platform. The data-reuse exploration problem is mathematically formulated and shown to be equivalent to the multiple-choice knapsack problem. The solution to this problem for an application code corresponds to the decision of which array references are to be buffered on-chip and where loading reused data of the array references into on-chip memory happen in the code, in order to minimise power consumption for a fixed on-chip memory size. The authors also present an experimentally verified power model, capable of providing the relative power information between different data-reuse design options of an application, resulting in a fast and efficient design-space exploration. The experimental results demonstrate that the approach enables us to find the most power-efficient design for all the benchmark circuits tested.
引用
收藏
页码:235 / 246
页数:12
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