Analytical Modelling and Analysis of Spacer Induced Shallow Source/Drain Extension Junction-Less Double Gate (SDE-JLDG) MOSFET Incorporating Fringing Field Effects

This paper is an unique attempt to analytically investigate a novel shallow source/drain extension junctionless double gate (SDE-JLDG) MOSFET. A two dimensional surface potential model for SDE-JLDG MOSFET has been derived by amalgamating gate fringing field effects using 2D Poisson's equation along with conformal mapping technique. Further, high-k spacers have been used to improve the device characteristics. The variation of potential along the channel for different high-k spacers has been demonstrated. In addition, extensive analysis of analog/RF behaviour and the effect of high-k spacer on various electrostatic, analog and RF parameters has also been demonstrated for the first time. The results shows that by using hafnium oxide (HfO2) as a high-k spacer provides higher immunity to short channel effects. SDE-JLDG MOSFET presents a good solution to improve the RF behaviour and provides a cost-effective high-performance analog/RF circuits.