Automatic generation of split-radix 2-4 parallel-pipeline FFT processors: Hardware reconfiguration and core optimizations

The results presented in the article are based on a methodology for automatic synthesis of real-time split radix 2-4 parallel-pipeline FFT-processors at structural level. The approach is oriented at reconfigurable FPGA-aware design and allows taking into account real-time application restrictions (input data structure and format, operating frequency, transform size, overall throughput) as well as other design restrictions (CLB-count area, power dissipation). The considered design examples prove method's good abilities for hardware optimization. Variants of split radix 2-4 computing element implementation are compared. Switching over from floating point arithmetics to fixed point data and the corresponding accuracy issues are considered.