A 16-Core Processor With Shared-Memory and Message-Passing Communications

被引：12

作者：

Yu, Zhiyi ^{[1
]}

Xiao, Ruijin ^{[2
]}

You, Kaidi ^{[3
]}

Quan, Heng ^{[4
]}

Ou, Peng ^{[1
]}

Yu, Zheng ^{[1
]}

He, Maofei ^{[1
]}

Zhang, Jiajie ^{[1
]}

Ying, Yan ^{[1
]}

Yang, Haofan ^{[5
]}

Han, Jun ^{[1
]}

Cheng, Xu ^{[1
]}

Zhang, Zhang ^{[6
]}

Jing, Ming'e ^{[1
]}

Zeng, Xiaoyang ^{[1
]}

机构：

[1] Fudan Univ, State Key Lab ASIC & Syst, Shanghai 201203, Peoples R China

[2] Bosera Asset Management Co Ltd, Res Dept, Shenzhen 518040, Peoples R China

[3] Marvell Technol Ltd, Shanghai 201203, Peoples R China

[4] Parade Technologies Inc, Shanghai 200233, Peoples R China

[5] Univ Toronto, Dept Elect & Comp Engn, Toronto, ON M5S 1A1, Canada

[6] Hefei Univ Technol, Hefei 230009, Peoples R China

来源：

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS | 2014年 / 61卷 / 04期

基金：

中国国家自然科学基金;

关键词：

Chip multiprocessor; cluster-based; FFT; H.264; decoder; inter-core communication; inter-core synchronization; LDPC decoder; LTE channel estimator; message-passing; multi-core; network-on-chip; NoC; shared-memory; SIMD; MICROPROCESSOR; ALGORITHM;

D O I：

10.1109/TCSI.2013.2283693

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A 16-core processor with both message-passing and shared-memory inter-core communication mechanisms is implemented in 65 nm CMOS. Message-passing communication is enabled in a 3 6 Mesh packet-switched network-on-chip, and shared-memory communication is supported using the shared memory within each cluster. The processor occupies 9.1 mm(2) and operates fully functional at a clock rate of 750 MHz at 1.2 V and maximum 800 MHz at 1.3 V. Each core dissipates 34 mW under typical conditions at 750 MHz and 1.2 V while executing embedded applications such as an LDPC decoder, a 3780-point FFT module, an H. 264 decoder and an LTE channel estimator.

引用

页码：1081 / 1094

页数：14

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