Quick Thermal Performance Estimation of Chip Scale Packaged GaN FETs using a Simple Circuit Model

We present a reduced physics-based thermal model to predict the thermal performance of Chip Scale Package (CSP) GaN FETs mounted to printed circuit boards (PCBs) and provide an easy-to-use thermal characterization tool for engineers and designers to quickly assess thermal management strategies. The heat conductance from the GaN FET to both the PCB side and to the "case" (i.e., die exposed surface) are modeled using resistive-network circuit modeling. The thermal resistance in each conductance path is presented for different parameters relating to PCB construction (stack-up, area, via density), FET size, and cooling approach (TIM material, heat spreader and heatsink). A comprehensive set of thermal finite-element simulations was run over the set of parameters. The results, presented in easy "look-up" style graphs, show that even with a small footprint, GaN FETs power-handling capability can be extended when effectively cooled using a simple PCB design and thermal management approach.