An Interface for the I2C Protocol in the WaferBoard™

This paper presents a circuit proposed for the DreamWafer (TM) technology. This circuit can interconnect several pads, also called NanoPads, in such a way that they can imitate the behavior of a single metal line for open-drain (or open-collector) buses compliant to the (IC)-C-2 protocol. Thus, multiple serial data lines (SDA) and serial clock lines (SCL) from different user ICs can be connected together on the Waferboard (TM). The interface can support up to 25 (IC)-C-2 IC pins together. It can support bidirectional data transfers at up to 100 kbit/s in the Standard-mode, up to 400 kbit/s in the Fast-mode, up to 1 Mbit/s in the Fast-mode Plus, or up to 3.4 Mbit/s in the High-speed mode. The entire interface would take less than 1% of the total area of the WaferIC (TM),the target system environment for which this circuit is proposed.