Test of a new sub 90 nm DR overlay mark for DRAM production

被引：2
|
作者：
Gruss, S [1 ]
Teipel, A [1 ]
Fülber, C [1 ]
机构：
[1] Infineon Technol, D-01099 Dresden, Germany
来源：
METROLOGY, INSPECTION, AND PROCESS CONTROL FOR MICROLITHOGRAPHY XVIII, PTS 1 AND 2 | 2004年 / 5375卷
关键词：
metrology; overlay; semiconductor manufacturing; DRAM;
D O I：
10.1117/12.534518
中图分类号：
T [工业技术];
学科分类号：
08 ;
摘要：
An improved overlay mark design was applied in high end semiconductor manufacturing to increase the total overlay measurement accuracy with respect to the standard box-in-box target. A comprehensive study has been conducted on the basis of selected front-end and back-end DRAM layers (short loop) to characterize contributors to overlay error. This analysis is necessary to keep within shrinking overlay budget requirements.
引用
收藏
页码：881 / 892
页数：12
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