Coarse Granularity Data Migration Based Power Management Mechanism for 3D DRAM Cache

3D-stacked technology is a promising solution to improve the performance of on-chip memory system. In our work, a 3D DRAM Cache with high density and wide bandwidth is utilized as the Last Level Cache (LLC). With the same Cache area, a 3D DRAM Cache shows superior capacity, bandwidth, cost performance ratio to a SRAM Cache. However, 3D DRAM storage has a problem of high power consumption. The power consumption of die-stacked DRAM is 5x compared to plane DRAM. In order to solve this problem, we proposed a power management mechanism for 3D DRAM Cache in this paper. The core idea of our mechanism is closing the infrequent accessed banks for saving power consumption. We design and implement a trace-driven 3D DRAM Cache simulator based on DRAMSim2. Experiment result of SPEC CPU2006 shown that for most applications, some banks have little access during execution. We proposed a coarse granularity data migration based power management mechanism. Compared with the system without power management mechanism, the static power consumption of some application decreased to 0.75x, a portion of application reach to 0.375x.