Low complexity DCT engine for image and video compression

被引:5
|
作者
Jridi, Maher [1 ]
Ouerhani, Yousri [1 ]
Alfalou, Ayman [1 ]
机构
[1] ISEN Brest, L bIsen, Equipe Vis, CS Brest 42807, Brest, France
来源
关键词
DCT; Multistandard; Optimization; FPGA implementation; ALGORITHM;
D O I
10.1117/12.2006174
中图分类号
O43 [光学];
学科分类号
070207 ; 0803 ;
摘要
In this paper, we defined a low complexity 2D-DCT architecture. The latter will be able to transform spatial pixels to spectral pixels while taking into account the constraints of the considered compression standard. Indeed, this work is our first attempt to obtain one reconfigurable multistandard DCT. Due to our new matrix decomposition, we could define one common 2D-DCT architecture. The constant multipliers can be configured to handle the case of RealDCT and/or IntDCT (multiplication by 2). Our optimized algorithm not only provides a reduction of computational complexity, but also leads to scalable pipelined design in systolic arrays. Indeed, the 8 x 8 StdDCT can be computed by using 4 x 4 StdDCT which can be obtained by calculating 2 x 2 StdDCT. Besides, the proposed structure can be extended to deal with higher number of N (i.e. 16 x 16 and 32 x 32). The performance of the proposed architecture are better when compared with conventional designs. In particular, for N = 4, it is found that the proposed design have nearly third the area-time complexity of the existing DCT structures. This gain is expected to be higher for a greater size of 2D-DCT.
引用
收藏
页数:9
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