A 54mW 1.2GS/s 71.5dB SNDR 50MHz BW VCO-Based CT ΔΣ ADC Using Dual Phase/Frequency Feedback in 65nm CMOS

被引：0

作者：

Reddy, Karthikeyan ^{[1
]}

Dey, Siladitya ^{[1
]}

Rao, Sachin ^{[1
]}

Young, Brian ^{[1
]}

Prabha, Praveen ^{[1
]}

Hanumolu, Pavan Kumar ^{[2
]}

机构：

[1] Oregon State Univ, Sch EECS, Corvallis, OR 97331 USA

[2] Univ Illinois, Urbana, IL 61801 USA

来源：

2015 SYMPOSIUM ON VLSI CIRCUITS (VLSI CIRCUITS) | 2015年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A wide bandwidth VCO-based continuous-time Delta Sigma modulator that uses combined phase and frequency feedback to mitigate VCO non-linearity and ease DEM timing requirement is presented. Fabricated in 65nm CMOS process, the prototype modulator operates at 1.2GS/s and achieves 71.5dB SNDR in 50MHz bandwidth while consuming 54mW of power, which translates to an FoM of 176fJ/conv-step.

引用

页数：2

共 7 条

[1] A 0.02mm2 65nm CMOS 30MHz BW All-Digital Differential VCO-based ADC with 64dB SNDR
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[2] A 125MHz-BW 71.9dB-SNDR VCO-Based CT.S ADC with Segmented Phase-Domain ELD Compensation in 16nm CMOS
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[3] A 16-mW 78-dB SNDR 10-MHz BW CT ΔΣ ADC Using Residue-Cancelling VCO-Based Quantizer
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[4] A Programmable 8-bit, 10MHz BW, 6.8mW, 200MSample/sec, 70dB SNDR VCO-Based ADC Using SC Feedback for VCO Linearization
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[5] A 200MHz-BW 0.13mm2 62dB-DR VCO-Based Non-Uniform Sampling ADC with Phase-Domain Level Crossing in 65nm CMOS
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[6] A 1.2V 86dB SNDR 500kHz BW Linear-Exponential Multi-Bit Incremental ADC Using Positive Feedback in 65nm CMOS
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[7] A 0.039 mm2 Inverter-Based 1.82 mW 68.6 dB-SNDR 10 MHz-BW CT-ΣΔ-ADC in 65 nm CMOS Using Power- and Area-Efficient Design Techniques
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