A Low-Power RF/Analog Front-End Architecture for LF passive RFID tags with Dynamic Power Sensing

This paper presents a low power, low voltage RF/analog front-end architecture for LF RFID tags with a dynamic power sensing scheme. The front-end converts the incoming RF power into DC using a system that adjusts its performance according to the available RF power. The power sensing scheme, composed by a feedback system that "regulates" the RF clamp stage, improves the incoming available power to the system. All building blocks together with the RF air link and antenna interface were modeled using digital and electrical signals with high abstraction level, validating the architecture. Part of the proposed AFE architecture was silicon proven in a preliminary CMOS 0.18 mu m process test chip. This preliminary part includes the regulation stages and part of the RF section. It shows excellent results for a maximum of 3 mu A DC current consumption, over a wide range of input RF power.