Design and Investigation of the Junction-Less TFET with Ge/Si0.3Ge0.7/Si Heterojunction and Heterogeneous Gate Dielectric

To improve the on-state current and reduce the miller capacitance of the conventional junction-less tunneling field effect transistor (JLTFET), the junction-less TFET with Ge/Si0.3Ge0.7/Si heterojunction and heterogeneous gate dielectric (H-JLTFET) is investigated by the Technology Computer Aided Design (TCAD) simulation in this paper. The source region uses the narrow bandgap semiconductor material germanium to obtain the higher on-state current; the gate dielectric adjacent to the drain region adopts the low-k dielectric material SiO2, which is considered to reduce the gate-to-drain capacitance effectively. Moreover, the gap region uses the Si0.3Ge0.7 material to decrease the tunneling distance. In addition, the effects of the device sizes, doping concentration and work function on the performance of the H-JLTFET are analyzed systematically. The optimal on-state current and switching ratio of the H-JLTFET can reach 6 mu A/mu m and 2.6 x 10(12), which are one order of magnitude and four orders of magnitude larger than the conventional JLTFET, respectively. Meanwhile, the gate-to-drain capacitance, off-state current and power consumption of the H-JLTFET can be effectively suppressed, so it will have a great potential in future ultra-low power integrated circuit applications.